`timescale 1ns/1ps
module even_check_top;
    reg X,clock,reset;
    wire Z;

    always # 1 clock = ~clock;
    initial begin
        reset = 0;
        clock = 0;
        X = 0;
        # 2 reset =1;
        # 2 reset =0;
        # 2 X = 1;
        # 2 X = 0; 
        # 2 X = 1;
        # 2 X = 0;
        # 2 X = 1;
        # 2 X = 0; 
        # 2 X = 1;
        # 2 X = 0;
        # 2 X = 1;
        # 2 X = 1; 
        # 2 X = 1;
        # 2 X = 0;
        # 2 X = 1;
        # 2 X = 0; 
        # 2 X = 1;
        # 2 X = 0;
        # 4 $stop;
    end
    even_check ec(Z,X,clock,reset);
	initial
	begin
    	$dumpfile("test.vcd");
    	$dumpvars(0, ec);
 	end

endmodule


module even_check(Z,X,clock,reset);
    input X,clock,reset;
    output Z;
    reg [3:0]count;
    reg D1,D2;
    wire temp;
    assign temp = D1^D2;
    always @(posedge clock or posedge reset)
        if(reset)begin
            D1 <= 0;
            D2 <= 0;
            count <= 4'b0000;
        end
        else if(count==4'd8)begin
            count <= 4'b0001;
            D1 <= X;
            D2 <= 0;
        end
        else begin
            D1 <= X;
            D2 <= temp;
            count <= count + 3'b1;
        end
    assign Z = (count==4'd8)?temp:1'bz;   
endmodule
